Study of a SiGe-HBT-based 1:2 demultiplexer IC up to 100 Gb/s rate
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Abstract:
An ultra-high speed 1:2 demultiplexer for optical fiber communication systems is designed utilizing the IHP 0.25 μm SiGe BiCMOS technology. The latch of the demultiplexer core circuit is researched. Based on the current measurement condition, a high-gain and wide-bandwidth clock buffer is designed to drive large load. Transmission line theory for ultra-high speed circuits is used to design matching network to solve the matching problem among the input, output and internal signals. The transient analysis shows that this demultiplexer can demultiplex one 100 Gb/s input into two 50 Gb/s outputs. The chip area of it is 0.7 mm × 0.47 mm, the input and output data are both at 400 mVP-P PCML standard voltage level, and the power consumption of the IC is 900 mW at the power supply of ?4 V.
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Clc Number:
TN32
