New CMOS readout circuit with background suppression and CDS for infrared focal plane array applications
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Abstract:
A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm × 15 μm area and consumes less than 0.4 mW power. Charge storage capacity is 3 × 108 electrons. The function and performance of the proposed readout circuit have been verified by experimental results.
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Clc Number:
TN432
